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exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 xr16c872 rev. 1.00 dual uart with 1284 parallel port and plug-and-play controller features plug and play isa bus specification compliant - auto configuration - direct connection, needing no external buffers - resource data in external 4k eeprom - support 10-interrupts, irq3-7, irq9-12, irq15 manual configuration for standard com1-com-4 and lpt1-lpt2 ieee 1284 compliant - bidirectional host port - level ii electrical interface, needing no external transceivers - standard centronics/ecp/epp mode - 16-byte fifo in ecp mode description august 2003 the xr16c872 1 (872) is a dual universal asynchronous receiver and transmitter (uart) with a 1284 bi-directional parallel port and isa bus plug-and-play (pnp) interface. the pnp interface supports auto configuration for desktop and embedded pc computers. the host bus interface can also be configured to manually support standard pc addresses com1-4 and lpt1-2. the parallel port is compatible to ieee 1284 specification and supports compatible centronics, extended capability (ecp) and enhanced parallel port (epp) protocols. the uarts are software compatible to industry standard 16c550 and include enhanced features of 128 bytes of transmit and receive fifos, programmable transmit and receive fifo trigger levels, transmit and receive fifo counters, irda (infrared data association) encoder/decoder, automatic rts/cts hardware flow control with selectable hysteresis and automatic software (xon/xoff) flow control. on board status registers provide interrupt priorities, receive data errors and modem status. each channel has a programmable baud rate generator to provide data rates up to 460.8kbps. the bi- directional parallel port can be configured as a general purpose input/output interface or connected to a printer or portable storage devices. the 872 operates on a single +5v and +3.3 power supply. it is available in a small 100- pin qfp package and offers commercial and industrial temperature ranges. the chip is fabricated in an advanced cmos process to reduce power consumption. 1 covered by u.s. patent number 5,649,122 and patent pending. 2 windows is a trademark of microsoft corp. dual uart software compatible with 16c550 128-byte of transmit and receive fifos to reduce cpu bandwidth requirement fifo counters in transmitter and receiver automatic rts/cts flow control with hysteresis to increase data throughput irda infrared pulse shaping encoder/decoder for up to 115.2kbps data rate up to 460.8 kbps standard serial data rate +5v and +3.3v operation 100-pin quad flat package (14x20mm) reference pc isa card design available windows 2 95, 98 and nt4 drivers available applications multi-function pc/isa bus card with rs-232/ rs-422/rs-485 interface and printer/parallel port embedded systems portable infrared wireless systems high speed bidirectional parallel port high speed serial ports ordering information part number package operating temperature device status XR16C872CQ 100-lead qfp 0 c to + 70 c discontinued. no replacement available. xr16c872iq 100-lead qfp -40 c to + 85 c discontinued. no replacement available. visit exar web site at www.exar.com discontinued
xr16c872 2 rev. 1.00 visit exar web site at www.exar.com discontinued 100 pin pqfp (14x20x3 mm, 1.95 mm form) err# iochrdy selctin# autofd# strobe# select xr16c872 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dreq1 dreq3 dreq5 gnd xtal1 xtal2 man# eed eeclk eecs ria# cda# dsra# ctsa# rtsa# dtra# txa rxa vcc gnd rib# cdb# dsrb# ctsb# rtsb# dtrb# txb rxb ack# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 reset a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11/lpt a12/s4 a13/s3 gnd a14/s2 a15/s1 aen d7 d6 d5 d4 vcc gnd d3 d2 d1 d0 pdir pd7 pd6 pd5 vcc gnd pd4 pd3 pd2 pd1 pd0 vcc gnd init# pe busy 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 iow# ior# gnd irq9 irq7 irq6 irq5 irq4 irq3 tc vcc irq10 irq12 irq11 irq15 dack0# dack1# dack3# dack5# dreq0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 figure 1, package description (top view)
xr16c872 3 rev. 1.00 visit exar web site at www.exar.com discontinued figure 2, funtional block diagram with plug-and-play interface. txb, rxb, dtr#, rts#, etc. to isa bus to external eeprom to serial port a transceivers to parallel port printer d0-d7 a0-a15 aen ior# iow# iochrdy irq3-7,9-12,15 dreq0,1,3,5 dack0,1,3,5# tc eed eeclk eecs pd0-pd7 init# strobe# selctin# autofd# pdir pe select busy ack# err# uart channel b (same as channel a block) dtra# rtsa# dsra# ctsa# cda# ria# txa modem interface transmit fifo (128 bytes) transmit shift re g ister irda v1.0 encoder rxa receive fifo (128 bytes) receive shift re g ister irda v1.0 decoder uart channel a xtal1 (22.1184 mhz) xtal2 baud rate gen. 1284 bi-directional parallel port controller with level ii electrical interface isa bus plug-and-play controller divide by 3 osc./ buffer 7.3728 mhz uart control re g isters reset internal bus eeprom controller to serial port b transceivers man# vcc
xr16c872 4 rev. 1.00 visit exar web site at www.exar.com discontinued figure 3, funtional block diagram with manual configuration interface. txb, rxb, dtr#, rts#, etc. to isa bus to serial port a transceivers to parallel printer port d0-d7 a0-a10 aen ior# iow# iochrdy irq3 irq4 irq5 irq7 dreq3 dack3# tc s1 s2 s3 s4 s5 pd0-pd7 init# strobe# selctin# autofd# pdir pe select busy ack# err# uart channel b (same as channel a block) dtra# rtsa# dsra# ctsa# cda# ria# txa modem interface transmit fifo (128 bytes) transmit shift re g ister irda v1.0 encoder rxa receive fifo (128 bytes) receive shift re g ister irda v1.0 decoder uart channel a xtal1 (22.1184 mhz) xtal2 baud rate gen. 1284 bi-directional parallel port controller with level ii electrical interface isa bus interface controller divide by 3 osc./ buffer 7.3728 mhz uart control re g isters reset internal bus to serial port b transceivers hardwired or jumpers address decoder for com1-4 and lp1-2 gnd man#
xr16c872 5 rev. 1.00 visit exar web site at www.exar.com discontinued pin description signal type definition. the following signal type definitions are from the 872 device point of view. i standard input o standard active output ot24 tri-state output iop14 tri-state bi-directional input/output io24 tri-state bi-directional input/output host interface a0-a15 2-15 i isa bus address. all 16 bits are used during pnp auto configuration 17,18 sequence with external eeprom providing the resource data. in the manual configuration mode a0-a10 are used for decoding com1-4 and lpt1-2 addresses. after auto or manual configuration, bits a0-a2 select uart internal registers and a3-a10 are used to select uart a or b, or the 1284 printer port. d0-d7 30-21 io24 isa data bus. these are the eight three state data lines for transferring data to or from the controlling cpu. d0 is the least significant bit and the first data bit in a transmit or receive serial data stream. aen 19 i address enable. active high to validate a0-a15 address lines during direct memory access operation on the isa bus. connect to logic 0 when it is not used. ior# 99 i read strobe. a logic 0 transition on this pin will request the contents of an internal register defined by address bits a0-a2 for either uart channels a/b or a0-a1 for the printer port, be place onto d0-d7 data bus for a read cycle by the cpu. iow# 100 i write strobe. a logic 1 transition on this pin will transfer the data on the data bus (d0-d7), as defined by either address bits a0-a2 for uart channels a/b or a0-a1 for the printer port, into an internal register during a write cycle from the cpu. irq15 86 ot24 interrupt request lines. these are three state active high interrupt lines to irq12-10 87-89 controlling cpu when an interrupt request is generated by the uart irq9 97 channel a/b or 1284 printer port. irq3-7 92-96 dreq5 78 ot24 dma request channel 0,1,3 and 5. these are three state active high dreq3 79 outputs with internal weak pull down resistor. dma request is used dreq1 80 by the 1284 parallel port during ecp and fifo mode. dreq0 81 dack5# 82 i dma acknowledge channel 0,1,3 and 5. these are active low inputs dack3# 83 and are used by the 1284 parallel port during ecp and fifo mode. dack1# 84 dack0# 85 name pin # type pin description
xr16c872 6 rev. 1.00 visit exar web site at www.exar.com discontinued iochrdy 20 ot24 input/output channel ready. iochrdy is a three state active high output with an internal weak pull-up resistor. this pin goes low when 1284 parallel port requires additional clock during a read or write cycle. tc 91 i terminal count. tc is an active high input during dma cycle and when dack# is low to indicates data transfer is complete. reset 1 i system reset. reset is an active high input. a 40ns minimum pulse will reset the internal registers and outputs to the default state. the tx output is at logic 1 and rx input is internally held at logic 1 during reset. see xr16c872 reset conditions for details. xtal1 76 i crystal oscillator input. a 22.1184 mhz crystal must be connected to this input and xtal2 pin to form an internal oscillator circuit which provides the main clock to the the baud rate generators. an external clock of same frequency may be used instead. xtal2 75 o crystal oscillator output. the other side of the crystal is connected to this pin to form an internal crystal oscillator. eed 73 bidir eed is a bi-drectional serial data bus to the external 93c46 eeprom. eeclk 72 o eeclk is a 500khz clock output to the external eeprom for serial data timing reference. eecs 71 bidir eeprom chip select. eecs is an active high output to the external eeprom. during manual configuration mode, a logic 1 input will bypass the internal divide-by-3 clock circuit to the two uarts. man# 74 i manual configuration select. man# is an active low input that enables s1- s5 for selection of com1-4 and lpt1-2 or in embedded applications. 1284 controller interface pd7-pd0 32-34 iop14 parallel data bus. pd0-pd7 are three-state bi-drectional data lines to the 37-41 parallel port. pd0 is the least significant bit with pd7 being the most significant bit. pd0-pd7 are high current drive outputs and can connect to the printer/parallel connector without external buffers. ack# 51 ip24 acknowledge. ack# is an active low input with with an internal weak pull-up. it can be a general purpose input or line printer acknowledge signal. a logic 0 from the parallel/printer indicates successful data transfer to the print buffer. autofd# 46 iop14 autolinefeed. autofd# is an active low tri-state with an internal weak pull- up. it can be a general purpose i/o or automatic line feed. when this signal is low the printer should automatically line feed after each printed line. pdir 31 o parallel port direction indicator. pdir indicates the operating direction of the name pin type pin description
xr16c872 7 rev. 1.00 visit exar web site at www.exar.com discontinued parallel port. an output logic 0 indicates the parallel port is operating as an output port and a logic 1 indicates it is an input port. busy 50 ip24 busy is an active high printer busy indicator or general purpose input. generally, it is used as an input from the printer and a logic 1 indicates it is not ready. the input has an internal weak pull-up resistor. err# 52 ip24 err# is printer error indicator or a general purpose input. generally, it is used as an input from the printer and a logic 0 indicates it has an error condition. the input has a weak internal pull-up resistor. init# 45 iop14 init# is a printer initialization signal or a general purpose output. generally, it is used with the printer (active low) for system initialization or reset. the pin is a tri-state output and has an internal weak pull-up resistor. pe 49 ip24 pe is a signal from the printer indicating a paper empty condition or general purpose input. generally, it is used with a printer and a logic 1 indicates the printer is out of paper. this input has an internal weak pull-up resistor. select 48 ip24 select is the printer select status indicat to the host or general purpose input. normally this pin is connected to a printer output and a logic 0 indicates the ready status of the printer, i.e., on-line and/or on-line and ready condiftion. this pin has an internal weak pull-up resistor. selctin# 44 iop14 selctin# is a select signal to the printer or general purpose i/o pin. this pin can be read via bit-3 in the printer command register, or written via bit-3 in the printer control register. normally this signal is connected to a printer to select the printer with an active low signal. the pin is tri-state output and has an internal weak pull-up resistor. strobe# 47 iop14 strobe# is a data strobe output or general purpose i/o pin. normally this output is connected to a printer and indicates that valid data is available on the data bus (pd0-pd7). the pin is a tri-state output with an intenal weak pull- up resistor. modem or serial port interface rxa, rxb 63,53 i receive data a/b. serial receive data or ir pulses input to uart channel a and b. the rx signal to the uart should be a logic 1 state during reset, idle (no data) and sleep mode. during the local loop-back mode, the rx input pins are disabled and tx data is internally connected to the uart rx inputs. in the ir mode, this input is normally at logic 0. txa, txb 64,54 o transmit data a/b. serial transmitt data or ir pulses output from channel a and b. the normal output is a logic 1 for serial data during reset, idle (no data), sleep mode, or when the transmitter is disabled. during the local loop-back mode, the tx output pin is held at logic 1and internally it connects to rx input. name pin type pin description
xr16c872 8 rev. 1.00 visit exar web site at www.exar.com discontinued in ir mode, the output changes to a logic 0 after it is enabled (mcr bit 5=1). dtra#, 65, o data terminal ready a/b or general purpose output. dtra/b# are active dtrb# 55 llow and associated with uartchannel a and b. a logic 0 on indicates that uart a/b is ready. this pin is controlled via the mcr register for channel a/b. setting mcr bit-0 to logic 1 puts the output pin to logic 0. this pin will be a logic 1 after writing a logic 0 to mcr bit-0. this pin has no effect on the uart transmitter or receiver. rtsa#, 66, o request to send a/b or general purpose output. rtsa/b# are active low rtsb# 56 outputs and associated with uart channels a/b. writing a logic 1 to mcr bit-1sets the pin to a logic 0 and requests remote unit to send data. after a reset this pin is set to a logic 1. when auto rts flow control is enabled (efr bit-6=1), a logic 0 asks remote modem to send data and a logic 1 requests to suspend. the user must assert rts# after enabling auto rts flow control. ctsa#, 67, i clear to send a/b or general purpose input. ctsa/b# are active low ctsb# 57 inputs and associated with uart channels a and b. a logic 0 indicates the remote modem is ready for data. a level change on this input pin will generate a status change interrupt (msr bit-0). when auto cts flow control is enabled, a logic 1 suspends local data transmission and a logic 0 restarts the local transmitter. dsra#, 68, i data set read a/b or general purpose input. dsra/b# are active low inputs dsrb# 58 and associated with uartchannel a and b. a logic 0 on indicates the modem is ready for data exchange with the uart. a logic level change on this input pin will generate a status change interrupt (msr bit-1).this pin has no effect on the uarts transmit or receive operation. cda#, 69, i carrier detect a/b or general purpose input. cda/b# are active low inputs and cdb# 59 associated with uart channels a and b. a logic 0 on this pin indicates a carrier signal has been detected by the modem. a logic level change on this input pin will generate a status change interrupt (msr bit-3). this pin has no effect on the uarts transmit or receive operation. ria#, 70, i ring indicator a/b or general purpose input. ria/b# are active low inputs rib# 60 and associated with uart channels a and b. a logic 0 on indicates the modem has received a ringing signal from the telephone line. a logic 1 transition on this input pin will generate a status change interrupt (msr bit-2). this pin has no effect on uart's transmit or receive operation. vcc 25,35,42 pwr +5 volts power supply. 62,90 gnd 16,26,36,43 pwr signal ground. 61,77,98 name pin type pin description
xr16c872 9 rev. 1.00 visit exar web site at www.exar.com discontinued function description the xr16c872 (872) is a highly integrated chip combining the functionality of two xr16c850 enhanced uart, an ieee 1284 bi-directional printer interface, and the pc/isa bus plug-and-play (pnp) interface. the pnp interface meets the plug-and-play isa specification version 1.0a of may 5,1994. the pnp interface and the 1284 printer port are both clocked for maximum performance by an external crystal oscillator of 22.1184 mhz. this clock is then internally divided by three to obtain a 7.3728 mhz clock for the two uarts. cpu bus interface options the 872 has two data bus interface modes, pnp and manual. in pnp mode, the chip will interface to the pc/isa bus directly and automatically configure each uart and the1284 parallel port address and irq interrupt. figure 2 depicts the block diagram and interface. plug-and-play mode the pnp interface supports industry standard jumperless auto configuration procedure in the pc/isa bus system. with an external eeprom chip providing the resource data for each of the logical devices, it automatically negotiates with windows 95 or 98 operating system and configures the operating setting for each device. the pc host system identifies and configures each pnp device using a set of defined registers accessed on the isa bus through three 8-bit i/o ports. all pnp interfaces in the host system respond to these same i/o ports, so after first sending an initiation key in order to enable all the interfaces, each interface is then isolated through the isolation protocol. even though all interfaces initially respond to the isolation protocol, the protocol is accomplished in such a way that no bus contention will occur. after a given interface has been isolated it is then assigned a unique card select number (csn) so that there after the interface can be uniquely addressed. all pnp interfaces support a defined readable resource data structure that completely describes the total resources required and the options supported by the interface. resource requirements of each pnp interface are broken down into groupings called logical devices, each of which can be thought of as a separate device. the two 850 uart and the 1284 parallel data port are referred to as a logical device, for a total of three logical devices. when all resource requirements of the entire system are known, a process of resource arbitration is invoked on the host system under windows operating system to determine the resources to allocate to each device. finally, each devices resource usage is programmed through a set of configuration registers. some of these configuration registers are common to all logical devices but the bulk of the registers are accessed separately for each logical device in the interface, with each particular logical devices configuration registers being mapped into the pnp register set one at a time. after configuration is complete, each pnp interface is removed from configuration mode in order to prevent accidental erasure or modification of the interfaces configuration. to re-enable configuration mode, the initiation key must be re-issued. the 872 uses all 16 bit address lines (a0-a15) for address decoding and supports 10 irq's (irq3-7, 9- 12 and 15). application note #xxxx describes the operation of the pnp interface in more detail.
xr16c872 10 rev. 1.00 visit exar web site at www.exar.com discontinued manual configuration mode interface the 872 provides an input pin (man#) to bypass the auto configuration procedure. it changes address lines a12- a15 to manual configuration inputs s1-s4 and lpt. these inputs can be designed with external jumpers to select com1-com4 for the serial ports, and lpt1 or lpt2 for the 1284 printer port. manual configuration mode supports the standard pc com and lpt port addresses and associated irq. however, the address lines can be mapped to other memory space areas for embedded applications, more on this later. the 872 eliminates the external address decoding logic circuitry that is typically required. the manual configuration is selected by making the man# pin logic 0 (gnd). this changes five address lines to become configuration inputs. the manual configuration is accomplished by decoding the pc isa bus address bits, a3 through a10 inside the 872 for chip select. these addresses select the uart for standard pc com ports: com- 1, com-2, com-3, com-4 and lpt-1 and lpt-2. five inputs (s1-s5) are generally externally jumper or wired to logic 1 or logic 0 for the operating port. the configuration inputs are also associated with a given pc interrupt. the mapping for the com port 1-4 and their associated interrupt selections are listed in table 1. besides the com port addresses, the 872 also decodes two parallel or printer addresses. the chip can be mapped into an embedded system memory space. figure 4 shows an example of wiring s1-s5 for default port configuration with irqa and irqb for the 2 uarts, and irqc with dreq, and dack for the parallel port. address lines a3-a10 are connected to the embedded system address lines a8-a15 instead, mapping it to address location 0x7f08-7f0f, 0x5f00-5f08, and 0x6f00-6f08 respectively. application note #xxxx describes how to design with manual configuration mode in more detail. man# s1 s2 s3 s4 s5 a3-a9 com port irq device selected 0 0 0 x x x 3f8-3ff com-1 irq4 uart channel a 0 1 0 x x x 2f8-2ff com-2 irq3 uart channel a 0 0 1 x x x 3e8-3ef com-3 irq4 uart channel a 0 1 1 x x x 2e8-2ef com-4 irq3 uart channel a 0 x x 0 0 x 3f8-3ff com-1 irq4 uart channel b 0 x x 1 0 x 2f8-2ff com-2 irq3 uart channel b 0 x x 0 1 x 3e8-3ef com-3 irq4 uart channel b 0 x x 1 1 x 2e8-2ef com-4 irq3 uart channel b 0 xxxx1 378-37f lpt-1 irq7 1284 parallel port 0 xxxx0 278-27f lpt-2 irq5 1284 parallel port x: don't care table 1, manual configuration mode internal addess decode
xr16c872 11 rev. 1.00 visit exar web site at www.exar.com discontinued man# 74 s3 16 s5 14 gnd s1 18 s2 17 s4 15 vcc to cpu bus mapped with address a8-a15: * uart-a at 0x7f00-7f08 & irqa * uart-b at 0x5f00-6f08 & irqb * 1284 port at 0x6f00-6f08 with irqc, dreq and dack# xr16c872 d0-d7 a0-a2 ior# iow# iochrdy tc port confi g uration lo g ic irq3 irq4 92 93 irqb (uart-b) irqa (uart-a) 94 95 96 97 irqc (1284) irq7 dreq (1284 port) dack# (1284 port) 89 88 87 86 81 80 79 84 83 82 78 85 dreq3 dack3# uart-a uart-b 1284 parallel port gnd aen# 91 20 100 99 19 2-4 30-21 a0-a2 a8-a15 a3-a10 5-12 figure 4, manual configuration interface in embedded application
xr16c872 12 rev. 1.00 visit exar web site at www.exar.com discontinued uart the 872 uarts are software compatible with the industry standard 16c550 on power up or reset. each uart offers enhancements that are enabled through its enhanced features registers. these features include transmit and receive fifos of 128 bytes, programmable transmit and receive fifo trigger level from 0 to 128, baud rates with 1x or 4x clock pre-scaler, automatic rts flow control level with trigger hysteresis, automatic cts flow control, automatic software flow control, modem or general i/o interface control, infrared irda encoder/ decoder select with a software option of inverting the decoder input logic level, sleep mode, device id and revision. the baud rate generator input clock on both uarts is supplied by a 7.37 28 mhz clock. this clock comes from an internal divided by 3 circuit that is fed by the crystal oscillator or external clock input of 22.1184 mhz. hence, the maximum operating data rate is 460.8 kbps. each uart provides 128 bytes of transmit and receive fifo memory instead of 16 in the 16c550. the larger fifo greatly reduces the bandwidth requirement of the controlling cpu, increases system performance with- out increasing the speed of the cpu, and reduces overall power consumption. the 128 byte fifos also simplify software manipulation of flash memory data transfer where data page size is 128 bytes. increased performance is realized by the larger transmit and receive fifos, fifo counters, and programmable fifo trigger level. this allows the processor to handle more networking tasks within a given time. for example, the 16c550 with 16 byte receive fifo, will require 1.39 milliseconds to unload the fifo (this example uses a character length of 10 bits, including start/stop bits at 115.2kbps, [1/115200]x10x16). this means the exter- nal cpu will have to service the receive fifo every 1.39 milliseconds. however with the 128 byte fifo in the 872 uart, the data buffer will not require unloading/loading for 11.12 milliseconds. this increases the service interval giving the cpu additional time for other applica- tions and reducing the overall uart interrupt servicing time. in addition, the fifo counters and programmable fifo trigger level interrupt is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. uart internal registers each 872 uart has 24 internal registers for monitoring and control. these resisters are summarized in table 2 below. twelve registers are compatible to those already in the standard 16c550. these registers function as data holding registers (thr/rhr), interrupt status and control registers (ier/isr), a fifo control register (fcr), control register and line status register, (lcr/ lsr), modem control and status registers (mcr/msr), programmable baud rate control registers (dll/dlm), and an user defined scratch pad register (spr). beyond the basic 16c550 features and capabilities, the 872 uart offers enhanced feature register set called trg, fctr, efr, xon1/2, xoff1/2, emsr, txcnt,rxcnt, rev and did, register functions are fully described in the following paragraphs.
xr16c872 13 rev. 1.00 visit exar web site at www.exar.com discontinued a2 a1 a0 read mode write mode basic registers (thr/rhr, fcr, ier/isr, mcr/msr, lcr/lsr, spr/fcnt), accessible only when lcr bit-7 is set to logic 0. 0 0 0 receive holding register transmit holding register 0 0 1 interrupt enable register interrupt enable register 0 1 0 interrupt status register fifo control register 0 1 1 line control register line control register 1 0 0 modem control register modem control register 1 0 1 line status register line status register 1 1 0 modem status register modem status register 1 1 1 scratch pad register scratch pad register 1 1 1 fifo counter (with fctr bit-6=1) baud rate registers (dll, dlm), accessible only when lcr bit-7 is set to a logic 1. 0 0 0 lsb of divisor latch lsb of divisor latch 0 0 0 device revision (see text) 0 0 1 msb of divisor latch msb of divisor latch 0 0 1 device identification (see text) enhanced registers (trg, fctr, efr, xon/xoff 1-2), accessible only when lcr is set to 0xbf. 0 0 0 fifo trigger register fifo trigger counter 0 0 1 feature control register feature control register 0 1 0 enhanced feature register enhanced feature register 1 0 0 xon-1 word xon-1 word 1 0 1 xon-2 word xon-2 word 1 1 0 xoff-1 word xoff-1 word 1 1 1 xoff-2 word xoff-2 word enhanced mode select register (emsr), accessible only when the fctr bit-6 is set to logic 1. 1 1 1 --- enhanced mode select register table 2, internal registers
xr16c872 14 rev. 1.00 visit exar web site at www.exar.com discontinued fifo operation the 128 byte transmit and receive data fifos are enabled by the fifo control register (fcr) bit-0. the standard 16c550 provides only receive fifo of 16 bytes with 4 selectable trigger levels and there is no transmit trigger level selection. the 872 uart provides independent programmable trigger levels from 0 to 128 for both receiver and transmitter. when receive or transmit data has reached the preset trigger level the uart generates an interrupt to call for service. the receive fifo section includes a time-out function to ensure data is delivered to the cpu. a receive data time-out interrupt is generated when there is no receive data for a period of about 4-characters but the receive holding register (rhr) is full or data did not reached the receive trigger level. see in the timing diagram area for tx and rx fifo operation. hardware (rts/cts) flow control operation automatic hardware or rts and cts flow control is used to prevent data overrun to the local receiver fifo and remote receiver fifo. the rts# output pin is used to request remote unit to suspend/restart data transmission while the cts# input pin is monitored to suspend/restart local transmitter. the auto rts and auto cts flow control features are individually selected to fit specific application requirement and enabled through efr bit-6 and 7. the auto rts function must be started by asserting rts# pin (mcr bit-1=1) after it is enabled. the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to send data (3). txb data arrives and fills uart-a receive fifo (4). when rxa data fills to up its receive fifo trigger level, uarta activates its rxa data ready interrupt (5) and continues to receive and put data into its fifo. if interrupt service latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper threshold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. uart-b stops or finishes sending the data bits in its transmit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-assert rtsa# (10) ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next rx trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold byte byte byte byte starts byte char char char char byte byte byte byte byte byte byte char char char char char char on off on assert rts# to begin transmission char char byte char char 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 char receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12
xr16c872 15 rev. 1.00 visit exar web site at www.exar.com discontinued two interrupts associated with rts and cts flow control have been added to give indication when rts# pin or cts# pin is de-asserted during operation. the rts and cts interrupts must be first enabled by efr bit-4, and then enabled individually by ier bit-6 and 7. automatic hardware flow control is selected by setting bits 6 (rts) and 7 (cts) of the efr register to logic 1. if cts# pin transitions from logic 0 to logic 1 indicating a flow control request, isr bit-5 will be set to logic 1 (if enabled via ier bit 6-7), and the 872 uart will suspend tx transmissions as soon as the stop bit of the character in process is shifted out. transmission is resumed after the cts# input returns to logic 0, indicating more data may be sent. the 872 uart offers a programmable flow control trigger hysteresis while maintains compatibility to 16c650a. with the auto rts function enabled, an interrupt is generated when receive fifo reaches the programmed rx trigger level. the rts# pin will not be forced to logic 1 (rts off) until it has reached the upper limit of the hysteresis level. this delay action of suspending remote transmitter increases data throughput. the rts# pin will return to a logic 0 (rts on) after rx data buffer (fifo) is unloaded to the lower limit of the hysteresis level. under these described conditions the uart will continue to accept data until receive fifo gets full. the auto rts function must be started by asserting rts# pin to logic 0 (rts on). for a full description of the hysteresis selection, see emsr bit 4 and 5 descriptions. software flow control when software flow control is enabled, the 872 uart compares one or two sequential receive data characters with the programmed xon or xoff-1,2 character value(s). if receive character(s) match the programmed values, the transmitter will halt transmission as soon as the current character has completed sent out. when a match occurs, the xoff-det interrupt (if enabled via ier bit-5) flag will be set and the interrupt output pin will be activated. following a suspension due to a match of the xoff characters values, the uart will monitor the receive data stream for a match to the xon-1,2 character value(s). if a match is found, the uart will resume operation and clear the xoff-det flag (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to logic 0. following reset the user can writes any xon/xoff value desired for software flow control. different conditions can be set to detect xon/xoff characters and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the 872 uart compares two consecutive receive characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmissions accordingly. under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible rx data fifo. if the receive fifo is overfilling and flow control needs to be executed, the 872 uart automatically sends a xoff message via the serial tx output to the remote modem. the 872 uart sends the xoff-1,2 characters as soon as received data passes the programmed rx fifo trigger level. to clear this condition, the 872 uart will transmit the programmed xon-1,2 characters as soon as receive data in the fifo drops below the programmed rx fifo trigger level. special feature software flow control a special feature is provided to detect a 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character is detected, it will be placed on the user accessible data stack along with normal incoming rx data. this condition is selected in conjunction with efr bits 0-3. note that the regular software flow control should be turned off when using this special mode by setting efr bit 0-3 to logic 0.
xr16c872 16 rev. 1.00 visit exar web site at www.exar.com discontinued the uart compares each incoming receive character with xoff-2 data. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of special character. although the internal register table shows each register with eight bits of character information, the actual number of bits is dependent on the programmed word length. line con- trol register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also deter- mines the number of bits that will be used for the special character comparison. bit-0 in the x-registers corre- sponds to the lsb bit for the receive character. interrupts interrupt conditions and priorities are indicated in the interrupt status register (isr), see table 4. when the transmitter interrupt is enabled the uart will issue an interrupt to indicate that transmit holding register (thr) is empty. this interrupt must be serviced before continu- ing operations. the lsr register provides the current singular highest priority interrupt only. it could be noted that cts and rts interrupts have lowest interrupt priority. a condition can exist where a higher priority interrupt may mask the lower priority cts/rts interrupt(s). only after servicing the higher pending interrupt will the lower priority cts/ rts interrupt(s) be reflected in the status register. servicing the interrupt without investigating further interrupt conditions can result in data errors. when two interrupt conditions have the same priority, it is important to service these interrupts correctly. re- ceive data ready and receive time out have the same interrupt priority (when enabled by ier bit-0). the receiver issues an interrupt after the number of charac- ters have reached the programmed trigger level. in this case the receive fifo may hold more characters than the programmed trigger level. following the removal of a data byte, the user should recheck lsr bit-0 for additional characters. a receive time out will not occur if the receive fifo is empty. the time out counter is reset at the center of each stop bit received or each time the receive holding register (rhr) is read. the actual time out value is t ( t ime out length in bits) = 4 x p ( p rogrammed word length) + 12. to convert the time out value to a character value, the user has to consider the complete word length, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1x, 1.5x, or 2x bit times. example -b: if the user programs the word length = 7, with parity and one stop bit, the time out will be: t = 4 x 7(programmed word length) + 12 = 40 bit times. character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. programmable baud rate generator the 872 uart supports high speed modem technolo- gies that have increased input data rate by employing data compression schemes. for example a 33.6 kbps modem that employs data compression may require a 115.2 kbps input data rate. a 128.0 kbps isdn modem that supports data compression may need an input data rate of 460.8 kbps. the 872 uart supports standard data rate from 50 to 460.8 kbps with a main clock of 7.3728 mhz which is internally derived from the external crystal or clock of 22.1184 mhz. a single baud rate generator provides for each uart transmitter and re- ceiver. the 872 uart can be configured for internal or external clock operation. for internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant, 20-33pf loading capacitance) is connected externally between the xtal1 and xtal2 pin, see figure 5. alternatively, an external clock can be con- nected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. figure 5, crystal osc. ext. components xr16c872 xtal1 xtal2 22.1184mhz *22-33pf *22-33pf gnd gnd *consult with crystal manufacturer for the proper loading capacitance
xr16c872 17 rev. 1.00 visit exar web site at www.exar.com discontinued output output user user dlm dll baud rate baud rate 16 x clock 16 x clock program program mcr mcr divisor divisor value value bit-7=1 bit-7=0 (decimal) (hex) (hex) (hex) 50 200 2304 900 09 00 75 300 1536 600 06 00 150 600 768 300 03 00 300 1200 384 180 01 80 600 2400 192 c0 00 c0 1200 4800 96 60 00 60 2400 9600 48 30 00 30 4800 19.2k 24 18 00 18 7200 28.8k 16 10 00 10 9600 38.4k 12 0c 00 0c 19.2k 76.8k 6 06 00 06 38.4k 153.6k 3 03 00 03 57.6k 230.4k 2 02 00 02 115.2k 460.8k 1 01 00 01 figure 6, clock pre-scaler and baud rate generator circuitry baud rate generator baud clock to transmitter and receiver mcr bit-7=0 (default) mcr bit-7=1 7.3728 mhz. clock from osc. & divider pre-scaler divides by 1 dlm and dll re g isters pre-scaler divides by 4 table 3, baud rate generator standard programming table with 7.3728 mhz clock
xr16c872 18 rev. 1.00 visit exar web site at www.exar.com discontinued sleep. with efr bit-4 and ier bit-4 enabled (set to logic 1), the uart enters the sleep mode when no interrupt is pending and no activities on the modem port. if an external clock is supplied to the uart, you may want to stop it. the uart resumes normal operation when a rx characters start bit is detected, a change of state on any of the modem input pins rx, ri#, cts#, dsr#, cd#, or transmit data is loaded into the fifo by the user. it typically takes 30us for the crystal oscillator to restart from sleep mode depending on the crystal properties. this delay must be taken into consideration during design as receive character(s) may be lost. the number of characters lost depends on the operating data rate, more at higher data rate. if the sleep mode is enabled and the uart is awakened by one of the conditions described above, it will return to the sleep mode auto- matically after the last character is transmitted or read by the user and no interrupt pending. the chip will not enter sleep mode whiles an interrupt(s) is still pending and the oscillator would still be running. the uart stays in the sleep mode of operation until it is disabled by setting ier bit-4 to logic 0. example of sleep mode enable during initialization: write lcr with 0xbf ; access to efr registers set efr bit-4 to logic 1 ; enable non-550 functions ; in ier, efr and mcr registers write lcr with op.value ; point to basic registers set ier bit-4 to logic 1 ; set sleep mode ; service all pending interrupts ; no modem port activity ; enters sleep mode and stop ; the oscillator for lowest sleep current the following pins should idle at logic 1 state: rx a/b should be at logic 1 and data bus should be pull- down with ~47k resistors if the controller puts the data bus in tri-state condition. no input pins should be left floating. loopback mode the internal loopback capability allows on board diag- nostics. in this mode, the normal modem interface pins are disconnected and re-configured for loopback inter- nally. msr bits 4-7 are also disconnected. however, mcr register bits 0-3 can be used for controlling loopback diagnostic testing. in this mode, op1 and op2 in the mcr register (bits 0-1) control the modem ri# and cd# inputs respectively. mcr signals dtr# and rts# (bits 0-1) are used to control the modem cts# and the generator divides the input 16x clock by any divisor from 1 to 2 16 -1. the uart divides the input clock by 16. further division of this 16x clock provides two table rates to support low and high data rate applications using the same system design. the two rate tables are selectable through the internal register, mcr bit-7. setting mcr bit-7 to logic 1 provides an additional divide by 4 whereas, setting mcr bit-7 to logic 0 only divides by 1. (see table 3 and figure 6). the frequency of the internal sampling rate is exactly 16x (16 times) of the selected baud rate. customized baud rates can be achieved by selecting the proper divisor values for the msb and lsb sections of baud rate generator. programming the baud rate generator registers dlm (msb) and dll (lsb) provides the user capability for selecting the desired serial baud rate. table 3 shows the two selectable baud rate tables available with the 7.3728 mhz clock. the output data rate tolerance is determined by the frequency accuracy of the 22.1184mhz crystal or external clock. dma operation the fifo trigger level provides additional flexibility to the user for data block transfer operation. lsr bits 5-6 provide an indication when the transmitter is empty or has an empty location(s). the user can optionally operate the transmit and receive fifos in the dma mode (fcr bit-3). when transmit and receive fifos are enabled and the dma mode is deactivated (dma mode 0), the uart activates the interrupt output pin for each data transmit or receive operation. when dma mode is activated (dma mode 1), the user takes the advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the preset trigger level. in this mode, the uart asserts the interrupt output pin when characters in the transmit fifos are below the transmit trigger level, or the number of characters in the receive fifos are above the receive trigger level. transmit or receive dma operation is selected by emsr register bit 2. sleep mode the uarts are designed to operate with low power consumption. a sleep mode is included to further reduce power consumption when the chip is not being used. the operating parameters are maintained while in
xr16c872 19 rev. 1.00 visit exar web site at www.exar.com discontinued dsr# inputs respectively. the transmitter output (tx) and the receiver input (rx) are disconnected from their associated interface pins, and instead are connected together internally (see figure 7). the cts#, dsr#, cd#, and ri# are disconnected from their normal modem control inputs pins, and instead are connected internally to dtr#, rts#, op1# and op2#. loopback test data enters transmit holding register via the user data bus interface, d0-d7. the transmitter serializes the data and passes the serial data to the receive uart via the internal loopback connection. the receive uart converts the serial data back into parallel data that is then made available at the user data interface, d0-d7. the user optionally compares the received data to the initial transmitted data for verifying error free operation of the uart tx/rx circuits. in this mode, the receiver, transmitter and modem control interrupts are fully operational. however, the interrupts can only be read using lower four bits of the modem control register (mcr bits 0-3) instead of the four modem status register bits 4-7. the interrupts are still controlled by the ier. please note that op1# and op2# pins are not brought out and not available. figure 7, internal loop-back mode diagram d0-d7 ior# iow# aen iochrdy reset a0-a2 irqn tx a-b rx a-b data bus & control logic register select logic modem control logic interrupt control logic transmit fifo registers flow control logic transmit shift register receive fifo registers flow control logic receive shift register inter connect bus lines & control signals baud rate generator cts# a-b rts# a-b dtr# a-b dsr# a-b ri# a-b cd# a-b (op1#) (op2#) mcr bit-4=1 eedio eeclk eecs eeprom controller irda decoder irda encoder clock
xr16c872 20 rev. 1.00 visit exar web site at www.exar.com discontinued 1234567890 1 23456789 0 1 23456789 0 1234567890 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1234567 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1234567 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1234567 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1234567 1234567 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1 23456 7 1234567 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 register functional descriptions the following table delineates the assigned bit functions for the internal registers. uart a and b has same register set independently control. the assigned bit functions are defined in the following paragraphs. uart internal registers a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 [default] note *3 basic registers are accessible when lcr bit-7 is set to logic 0. (shaded bits are enabled by efr bit-4) 0 0 0 rhr [xx] b it-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 thr [xx] b it-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier [00] 0/ 0/ 0/ 0/ modem receive transmit receive cts# rts# xoff sleep status line holding holding interrupt interrupt interrupt mode interrupt status register register interrupt 0 1 0 fcr [00] rcvr rcvr 0/tx 0/tx dma xmit rcvr fifo trigger trigger trigger trigger mode fifo fifo enable (msb) (lsb) (msb) (lsb) select reset reset 0 1 0 isr [01] 0/ 0/ 0/ 0/ int int int int fifos fifos rts#, xoff priority priority priority status enabled enabled cts# det. bit-2 bit-1 bit-0 0 1 1 lcr [00] d ivisor set set even parity stop word word latch break parity parity enable bits length length enable b it-1 bit-0 1 0 0 mcr [00] clock 0/ 0/ loop (op2#) (op1#) rts# dtr# select irrt xon-any back enable 1 0 1 lsr [60] 0/ trans. trans. break framing parity ove rrun receive fifo shift reg. holding interrupt error error error data error empty reg. empty ready 1 1 0 msr [00] cd# ri# dsr# cts# delta delta delta delta cd# ri# dsr# cts# 1 1 1 spr [ff] or bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 fifo count baud rate generator registers are accessible only when lcr bit-7 is set to a logic 1. 0 0 0 dll [xx] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 dlm [xx] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8
xr16c872 21 rev. 1.00 visit exar web site at www.exar.com discontinued 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 uart internal registers (continue) a2 a1 a0 register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 [default] note *3 enhanced registers are accessible only when lcr is set to 0xbf. 0 0 0 trg [00] trig/ trig/ trig/ trig/ trig trig/ trig/ trig/ fc fc fc fc fc fc fc fc 0 0 1 fctr [00] r x/tx spr/emsr trig trig rs485 irrx rts rts mode select bit-1 bit-0 auto inv. hysteresis hysteresis control bit-1 bit-0 0 1 0 efr [00] auto auto special enable cont-3 cont-2 cont-1 cont-0 cts rts char. ier bits tx,rx tx,rx tx,rx tx,rx select 4-7, co ntrol control control control isr, fcr bits 4-5, mcr bits 5-7 1 0 0 xon-1[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon-2[00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 1 1 0 xoff-1[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff-2[00] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 emsr register is accessible only when fctr bit 6 is set to logic 1. 1 1 1 emsr [00] not not rts rts reserved reserved alt. rx/tx used used hysteresis hysteresis rx/tx fifo bit-3 bit-2 fifo count count note *3: the value represents the registers initialized hex value. an x signifies a 4-bit un-initialized nibble.
xr16c872 22 rev. 1.00 visit exar web site at www.exar.com discontinued the uarts have device identification and device revision code to distinguish the part with others. it is suggested to the user to read the identification and revision information from the part only during the power on initialization routine to avoid disturbing the baud rate generator during normal operation. to read the identification number from the device, it is required to set the baud rate generator divisor latch to logc 1 (lcr bit-7 = logic 1) and set the content of the baud rate generator dll and dlm registers to 0x00. then read the content of dlm=0x10 for xr16c850 type and the content of dll for the device revision with 0x01 represents revision-a and 0x02 for revision-b, and so forth. at the beginning of uart initiation routine: write lcr bit-7=1 write dlm = 0x00 write dll = 0x00 read dlm for the uart type number (0x10) read dll for the uart revision number (0x02) transmit and receive data register the serial transmitter section consists of a 8-bit transmit hold register (thr) which is part of the transmit fifo and transmit shift register (tsr). the status of the thr and tsr are provided in the line status register (lsr). writing to thr address location transfers the contents of the data bus (d7-d0) to the thr, providing that the thr or tsr flag is set. the thr empty flag is set to logic 1 when the transmit fifo has room for more data. the flag indicates either that the transmit holding register becomes empty in the non-fifo mode or at the preset transmit trigger level when the transmit fifo is enabled. the tsr flag always indicates the transmitter is empty and it has nothing to shift out. this flag can be use for directional control in half duplex operations. the serial receive section also contains a 11-bit receive holding register (rhr) which is part of the receive fifo. receive data is unloaded by reading the rhr register address location. the receive section provides a mechanism to detects false starts. on the falling edge of a start or false start bit on rx input, an internal sampling counter starts counting clocks at 16x of the operating data rate. after 7 1/2 clocks the incoming start bit time should be at the center of the bit time. at this time the start bit is sampled and if it is still a logic 0 it is validated. if false, the detection sequence starts all over again. evaluating the start bit in this manner and validating data bits and stop bit also in the middle of the bit time helps to ensure the integrity of the receiving character. receive errors such as framing, parity, and overrun are saved in the receive fifo and posted in the lsr upon each data byte becomes available to the cpu. the receive fifo is actually a 11-bit wide fifo including the 3 receive error bits. the receiver fifo pointer is bumped upon a data byte read operation. therefore, it is necessary for the user to read the error bits prior reading the data byte. interrupt enable register (ier) the interrupt enable register (ier) masks the inter- rupts for receiver ready, transmitter empty, line status, and modem status. it also optionally includes cts#, rts# and xoff interrupts when enabled by efr register bit-4. these interrupts are wired ored to the int output pin. see ier register description for more detail. receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = logic 1) and receive interrupt (ier bit-0 = logic 1) are enabled, the receive interrupt and register status will reflect the following: a) the receive data interrupt is issued when the receive fifo has reached the programmed trigger level. the interrupt clears when 1) upon reading lsr register or 2) fifo content drops below the programmed trigger level. b) receive fifo status is also reflected in the isr register when the fifo trigger level has reached the programmed level. the isr register status bit will clear only when the fifo content drops below the pro- grammed trigger level. c) the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the receive shift register to the receive fifo. this bit is reset when the fifo becomes empty.
xr16c872 23 rev. 1.00 visit exar web site at www.exar.com discontinued receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1; resetting ier bits 0- 3 enables the 850 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a) lsr bit-0 will be a logic 1 as long as there is one byte in the receive fifo. b) lsr bit 1-4 will indicate if an overrun error occurred in the receiver. c) lsr bit-5 will indicate when the transmit fifo is empty. d) lsr bit-6 will indicate when both the transmit fifo and transmit shift register are empty. e) lsr bit-7 will indicate any data errors within the receive fifo. this bit will clear when the error byte is unloaded. ier bit-0: logic 0 = disable the receiver ready interrupt. (normal default condition) logic 1 = enable the receiver ready interrupt. the receiver ready interrupt is cleared when lsr is read. ier bit-1: logic 0 = disable the transmitter empty interrupt. (normal default condition) logic 1 = enable the transmitter empty interrupt. the transmitter empty interrupt is cleared when isr is read. ier bit-2: logic 0 = disable the receiver line status interrupt. (normal default condition) logic 1 = enable the receiver line status interrupt. the receiver line interrupt is cleared when lsr is read. ier bit-3: logic 0 = disable the modem status register interrupt. (normal default condition) logic 1 = enable the modem status register interrupt. the modem status interrupt is cleared when msr is read. ier bit -4: logic 0 = disable sleep mode. (normal default condi- tion) logic 1 = enable sleep mode. see sleep mode section for details. ier bit-5: logic 0 = disable the software flow control, receive xoff-det interrupt. (normal default condition) logic 1 = enable the software flow control, receive xoff-det interrupt. the xoff-det interrupt is cleared by reading the isr register or upon receiving a xon charac- ter. also, when special character mode is enabled (efr-bit 5 =1) reading the isr register or a following received character will clear the interrupt. ier bit-6: logic 0 = disable the rts interrupt. (normal default condition) logic 1 = enable the rts interrupt. the uart issues an interrupt when the rts# pin transitions from a logic 0 to a logic 1 as reported in msr bit-register. the interrupt is cleared by reading the msr register. ier bit-7: logic 0 = disable the cts interrupt. (normal default condition) logic 1 = enable the cts interrupt. the uart issues an interrupt when cts# pin transitions from a logic 0 to a logic 1 as reported in msr register. the interrupt is cleared by reading the msr register. fifo control register (fcr) this register is used to enable the fifos, clear the fifos, set the transmit/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: dma mode mode 0 set and enable the interrupt for each single character transmit or receive operation. transmit empty interrupt will be generated whenever the transmit hold- ing register (thr) is empty and receive ready interrupt will be generated whenever the receive holding regis- ter (rhr) is loaded with a character. however, the rx fifo continues to receive data up to its limit.
xr16c872 24 rev. 1.00 visit exar web site at www.exar.com discontinued mode 1 enable the interrupt in a block transfer mode operation. the transmit empty interrupt is set when the transmit fifo trigger level is reached. the receive interrupt is set when the receive fifo fills up to the programmed trigger level. however the fifo contin- ues to fill regardless of the programmed level until the fifo is completely full. fcr bit-0: logic 0 = disable the transmit and receive fifo. (normal default condition) logic 1 = enable the transmit and receive fifo. this bit must be a 1 when other fcr bits are written to or they will not be programmed. fcr bit-1: logic 0 = no fifo receive reset. (normal default condition) logic 1 = clears the fifo counter and resets the pointers logic (the receive shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. fcr bit-2: logic 0 = no fifo transmit reset. (normal default condition) logic 1 = clears the fifo counter and resets the pointers logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after clearing the fifo. fcr bit-3: logic 0 = set dma mode 0. (normal default condition) logic 1 = set dma mode 1. transmit operation in mode 0: this selects single character interrupt operation. the transmit empty interrupt will be set when the uart is set in this 16c450 or single character simulation mode (fifos disabled, fcr bit-0 = logic 0) or in the fifo mode (fifos enabled, fcr bit-0 = logic 1, fcr bit-3 = logic 0) and when there are no characters in the transmit fifo or transmit holding register. receive operation in mode 0: when the uart is in mode 0 (fcr bit-0 = logic 0) or in the fifo mode (fcr bit-0 = logic 1, fcr bit-3 = logic 0) and there is a character in rhr, the receive ready interrupt is generated. transmit operation in mode 1: when the uart is in fifo mode ( fcr bit-0 = logic 1, fcr bit-3 = logic 1 ), the transmit empty interrupt is generated when the transmit fifo reaches its trigger level. receive operation in mode 1: when the uart is in fifo mode (fcr bit-0 = logic 1, fcr bit-3 = logic 1) and the receive trigger level has been reached, or a receive time out has occurred, the receive ready interrupt is generated. fcr bit 4-5: (logic 0 or cleared is the default condition, tx trigger level = none) the xr16c850 provide 4 user selectable trigger levels, the fctr bits 4-5 selects one of the following table. these bits are used to set the trigger level for the transmit fifo interrupt. the uart will issue a transmit empty interrupt when number of characters in fifo drops below the selected trigger level. trigger table-a (transmit) default setting after reset, st16c550 mode bit-5 bit-4 fifo trigger level x x none trigger table-b (transmit) bit-5 bit-4 fifo trigger level 00 16 01 8 10 24 11 30 trigger table-c (transmit) bit-5 bit-4 fifo trigger level 00 8 01 16 10 32 11 56
xr16c872 25 rev. 1.00 visit exar web site at www.exar.com discontinued trigger table-d (receive) bit-7 bit-6 fifo trigger level x x user programmable trigger levels an example to program the fifo trigger level: write lcr with 0xbf ; point to enhanced registers set fctr bit4-5 to logic 1 ; select trigger table-d set fctr bit-7 to logic 0 ; program rx fifo trigger level write trg with 0x60 ; set your rx trigger level to 96 set fctr bit-7 to logic 1 ; program tx fifo trigger level write trg with 0x08 ; set your tx trigger level to 8 write lcr with 0x03 ; set operating parameters receive data ready interrupt will activates when rx fifo fills up to 96 data bytes while the transmit empty interrupt gets set when data is empty to 8 bytes. trigger table-d (transmit) bit-5 bit-4 fifo trigger level x x user programmable trigger levels fcr bit 6-7: (logic 0 or cleared is the default condition, rx trigger level =8) these bits are used to set the trigger level for the receiver fifo interrupt. the interrupt will trigger again when rx data got unloaded below the threshold and incoming data fill it back up to the trigger level. the fctr bits 4-5 selects one of the following table. trigger table-a (receive) default setting after reset, st16c550 mode bit-7 bit-6 fifo trigger level 00 1 01 4 10 8 11 14 trigger table-b (receive) bit-7 bit-6 fifo trigger level 00 8 01 16 10 24 11 28 trigger table-c (receive) bit-7 bit-6 fifo trigger level 00 8 01 16 10 56 11 60
xr16c872 26 rev. 1.00 visit exar web site at www.exar.com discontinued interrupt status register (isr) the uart provides six levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will provide the user with the highest pending interrupt level to be serviced. no other interrupts are acknowledged until the pending interrupt is serviced. whenever the interrupt status register is read, the interrupt status is cleared. however it should be noted that only the current pending interrupt is cleared by the read. a lower level interrupt may be seen after re- reading the interrupt status bits. the interrupt source table 6 (below) shows the data values (bit 0-5) for the six prioritized interrupt levels, the interrupt sources associated with each of these interrupt levels, and how to clear each interrupt (int). priority [ isr bits ] int clears level b it-5 bit-4 bit-3 bit-2 bit-1 bit-0 source of the interrupt after a 1 000110 lsr (receiver line status register) lsr read 2 000100 rxrdy (received data ready) lsr read 2 001100 rxrdy (receive data time out) lsr read 3 000010 txrdy ( transmitter holding register empty) isr read 4 000000 msr (modem status register) msr read 5 010000 rxrdy (rcv. xoff signal / special character) isr read 6 100000 cts, rts change of state msr read table 4, interrupt priority and source isr bit-0: logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. logic 1 = no interrupt pending. (normal default condition) isr bit 1-3: (logic 0 or cleared is the default condition) these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see interrupt source table). isr bit 4-5: (logic 0 or cleared is the default condition) these bits are enabled when efr bit-4 is set to a logic 1. isr bit-4 indicates that matching xoff character(s) have been received. isr bit-5 indicates that cts# or rts# condition have changed. note that once set to a logic 1, the isr bit-4 will stay a logic 1 until xon character(s) is received or upon a read to register isr. isr bit 6-7: (logic 0 or cleared is the default condition) these bits are set to a logic 0 when the fifo is not being used. they are set to a logic 1 when the fifos are enabled line control register (lcr) the line control register is used to specify the asynchronous data communication format. the word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. this register also has a secondary function to select 2 other register sets. the first is by setting bit-7 = 1 to select the baud rate divisor (dll and dlm) registers, and the second set of registers is selected when a bf hex is written to lcr to select the enhanced register set.
xr16c872 27 rev. 1.00 visit exar web site at www.exar.com discontinued lcr bit 0-1: (logic 0 or cleared is the default condition) these two bits specify the word length to be transmitted or received. the upper unused bit(s) in the received data byte is set to zero. bit-1 bit-0 word length 00 5 01 6 10 7 11 8 lcr bit-2: (logic 0 or cleared is the default condition) the length of stop bit is specified by this bit in conjunc- tion with the programmed word length. bit-2 word stop bit length length (bit time(s)) 0 5,6,7,8 1 1 5 1-1/2 1 6,7,8 2 lcr bit-3: parity or no parity can be selected via this bit. logic 0 = no parity (normal default condition) logic 1 = a parity bit is generated during the transmis- sion, the receiver checks and reports parity error in the lsr register. the parity is not presented in the received data byte. lcr bit-4: if the parity bit is enabled with lcr bit-3 set to a logic 1, lcr bit-4 selects the even or odd parity format. logic 0 = odd parity is generated by forcing an odd number of logic 1s in the transmitted data. the receiver must be programmed to check the same format. (normal default condition) logic 1 = even parity is generated by forcing an even the number of logic 1s in the transmitted. the receiver must be programmed to check the same format. lcr bit-5: if the parity bit is enabled, lcr bit-5 selects the forced parity format. lcr bit-5 = logic 0, parity is not forced (normal default condition) lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr lcr lcr parity selection bit-3 bit-4 bit-5 0 x x no parity 1 0 0 odd parity 1 1 0 even parity 1 0 1 force parity=1 1 1 1 forced parity= 0 lcr bit-6: when enabled the break control bit causes a break condition to be transmitted (the tx output is forced to a logic 0 state). this condition exists until disabled by setting lcr bit-6 to a logic 0. logic 0 = no tx break condition. (normal default condition) logic 1 = forces the transmitter output (tx) to a logic 0 for alerting the remote receiver to a line break condition. lcr bit-7: the internal baud rate counter latch and enhance feature mode enable. logic 0 = divisor latch disabled. (normal default condi- tion) logic 1 = select baud rate divisors (dll and dlm) and enhanced feature register set enabled modem control register (mcr) this register controls the interface with the modem or a peripheral device. mcr bit-0: logic 0 = force -dtr output to a logic 1. (normal default condition) logic 1 = force -dtr output to a logic 0. mcr bit-1: logic 0 = force rts# output to a logic 1. (normal default condition)
xr16c872 28 rev. 1.00 visit exar web site at www.exar.com discontinued logic 1 = force rts# output to a logic 0. automatic rts may be used for hardware flow control by enabling efr bit-6 (see efr bit-6). mcr bit-2: *op1# output is not available in the 872. logic 0 = set op1# output to a logic 1. (normal default condition) logic 1 = set op1# output to a logic 0. mcr bit-3: *op2# output is not available in the 872 logic 0 = set op2# output to a logic 1. (normal default condition) logic 1 = set op2# output to a logic 0. mcr bit-4: logic 0 = disable loop-back mode. (normal default condition) logic 1 = enable local loop-back mode (diagnostics). mcr bit-5: logic 0 = disable xon-any function (normal default condition) logic 1 = enable xon-any function. in this mode any rx character received will enable xon. mcr bit-6: logic 0 = enable modem receive and transmit input/ output interface. (normal default condition) logic 1 = enable infrared irda receive and transmit inputs/outputs. while in this mode, the tx/rx output/ inputs are routed to the infrared encoder/decoder. the data input and output levels will conform to the irda infrared interface requirement. as such, while in this mode the infrared tx output will be a logic 0 during idle data conditions. care must be taken into consideration in the design not to over heat the ir led during power up initialization state while tx output is still at logic 1. example to enable ir encoder and decoder. write lcr with 0xbf ; access to efr shadow register set efr bit-4 to logic 1 ; enable non-550 bits in ier, efr & mcr write lcr with op. value ; set up lcr and point to base register set set mcr bit-6 to logic 1 ; enable ir mode, tx output pin goes logic 0 mcr bit-7: logic 0 = divide by one. the input clock (crystal or external) is divided by sixteen and then presented to the programmable baud rate generator (bgr) without further modification, i.e., divide by one. (normal, default condition) logic 1 = divide by four. the divide by one clock described in mcr bit-7 equals a logic 0, is further divided by four (also see programmable baud rate generator section). line status register (lsr) this register provides the status of data transfers between the uart and the cpu. lsr bit-0: logic 0 = no data in receive holding register or fifo. (normal default condition) logic 1 = data has been received and is saved in the receive holding register or fifo. lsr bit-1: logic 0 = no overrun error. (normal default condition) logic 1 = overrun error. a data overrun error occurred in the receive shift register. this happens when additional data arrives while the fifo is full. in this case the previous data in the shift register is overwritten. note that under this condition the data byte in the receive shift register is not transfer into the fifo, therefore the data in the fifo is not corrupted by the error. lsr bit-2: logic 0 = no parity error (normal default condition) logic 1 = parity error. the receive character does not have correct parity information and is suspect. in the fifo mode, this error is associated with the character at the top of the fifo. lsr bit-3: logic 0 = no framing error (normal default condition). logic 1 = framing error. the receive character did not have a valid stop bit(s). in the fifo mode this error is associated with the character at the top of the fifo. lsr bit-4: logic 0 = no break condition (normal default condition) logic 1 = the receiver received a break signal (rx was a logic 0 for one character frame time). in the fifo mode, only one break character is loaded into the fifo.
xr16c872 29 rev. 1.00 visit exar web site at www.exar.com discontinued msr bit-0: logic 0 = no cts# change (normal default condition) logic 1 = the cts# input to the uart has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-1: logic 0 = no dsr# change (normal default condition) logic 1 = the dsr# input to the uart has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-2: logic 0 = no ri# change (normal default condition) logic 1 = the ri# input to the uart has changed from a logic 0 to a logic 1. a modem status interrupt will be generated. msr bit-3: logic 0 = no cd# change (normal default condition) logic 1 = indicates that the cd# input to the has changed state since the last time it was read. a modem status interrupt will be generated. msr bit-4: cts# functions as hardware flow control signal input if it is enabled via efr bit-7. the transmit holding register flow control is enabled/disabled by msr bit-4. flow control (when enabled) allows suspending and resum- ing data transmissions based on the external modem cts# signal. a logic 1 at the cts# pin will suspend transmissions as soon as current character has fin- ished transmission. normally msr bit-4 bit is the compliment of the cts# input. however in the loop-back mode, this bit is equivalent to the rts bit in the mcr register. lsr bit-5: this bit is the transmit holding register empty indica- tor. this bit indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to cpu when the thr interrupt enable is set. the thr bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. the bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the cpu. in the fifo mode this bit is set when the transmit fifo is empty; it is cleared when at least 1 byte is written to the transmit fifo. lsr bit-6: this bit is the transmit empty indicator. this bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmit fifo and transmit shift register are both empty. lsr bit-7: logic 0 = no error (normal default condition) logic 1 = there is at least one parity error, framing error or break indication is in the current fifo data. this bit is cleared when lsr register is read. when the lsr is read, bit 2,3 and 4 reflects the error bits of the character on top of the rx fifo, next character to be read in rhr. therefore, errors in a character are identified by reading the lsr and then reading the data character in rhr. modem status register (msr) this register provides the current state of the control interface signals from the modem, or other peripheral device that the uart a or b is connected. four bits of this register are used to indicate the changed informa- tion. these bits are set to a logic 1 whenever a control input from the modem changes state. these bits are set to a logic 0 whenever the cpu reads this register.
xr16c872 30 rev. 1.00 visit exar web site at www.exar.com discontinued msr bit-5: dsr (active high, logical 1). normally this bit is the compliment of the dsr# input pin. in the loop-back mode, this bit is the complement to the dtr bit in the mcr register. msr bit-6: ri (active high, logical 1). normally this bit is the compliment of the ri# input. in the loop-back mode this bit is equivalent to the op1# bit in the mcr register. msr bit-7: cd (active high, logical 1). normally this bit is the compliment of the cd# input. in the loop-back mode this bit is equivalent to the op2# bit in the mcr register. scratch pad register (spr) the uart a or b has a temporary data register to store 8 bits of user information. the register content is set to 0xff upon power up or a hardware reset. this register is alternately used as tx or rx fifo counter register, when fctr bit-6=1 with emsr bit-0 defining for txcnt or rxcnt. enhanced feature register (efr) this register is only accesible when lcr is set to 0xbf. enhanced feature functions in the 16c550 base register set area are enabled using this register bit-4. these are ier bits 4-7, isr & fcr bits 4-5, and mcr bits 5-7. bits-0 through 3 provide single or dual character software flow control selection. when the xon1 and xon2 and/or xoff1 and xoff2 modes are selected (see table 5), the double 8-bit words are concatenated into two sequential characters. efr bit 0-3: (logic 0 or cleared is the default condition) combinations of software flow control can be selected by programming these bits. cont-3 cont-2 cont-1 cont-0 tx, rx software flow controls 0 0 x x no transmit flow control 1 0 x x transmit xon1/xoff1 0 1 x x transmit xon2/xoff2 1 1 x x transmit xon1 and xon2/xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1/xoff1 x x 0 1 receiver compares xon2/xoff2 1011 transmit xon1/ xoff1. receiver compares xon1 and xon2, xoff1 and xoff2 0111 transmit xon2/xoff2 receiver compares xon1 and xon2/xoff1 and xoff2 1111 transmit xon1 and xon2/xoff1 and xoff2 receiver compares xon1 and xon2/xoff1 and xoff2 0011no transmit flow control receiver compares xon1 and xon2/xoff1 and xoff2 table 5, software flow control registers
xr16c872 31 rev. 1.00 visit exar web site at www.exar.com discontinued efr bit-4: enhanced function control bit. the content of the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 can be modified and latched. after modifying any bits in the enhanced registers, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents existing software from altering or overwriting the uart enhanced functions. logic 0 = disable/latch enhanced features. ier bits 4- 7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are saved to retain the user settings, then ier bits 4-7, isr bits 4- 5, fcr bits 4-5, and mcr bits 5-7 are initialized to the default values shown in the internal resister table. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, and mcr bits 5-7 are set to a logic 0 to be compatible with st16c550 mode. (normal default condition). logic 1 = enables the enhanced functions. when this bit is set to a logic 1 all enhanced features of the uart are enabled and user settings stored during a reset will be restored. efr bit-5: logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. the uart compares each incoming receive character with xoff-2 data. if a match exists, the received data will be transferred to fifo and isr bit-4 will be set to indicate detection of special character. bit-0 in the x-registers corresponds with the lsb bit for the receive character. when this feature is enabled, the normal software flow control must be disabled (efr bits 0-3 must be set to a logic 0). efr bit-6: automatic rts is used for hardware flow control by enabling efr bit-6. the user must assert rts# to initiate this function. when auto rts is selected, an interrupt will be generated when the receive fifo is filled to the programmed rx trigger level and rts# will go to a logic 1 when it reaches the upper limit of the hysteresis level. rts# will return to a logic 0 when data is unloaded to the lower limit of the hysteresis. the state of this register bit changes with the status of the hardware flow control. rts# functions normally when hardware flow control is disabled. 0 = automatic rts flow control is disabled. (normal default condition) 1 = enable automatic rts flow control. efr bit-7: automatic cts flow control. logic 0 = automatic cts flow control is disabled. (normal default condition) logic 1 = enable automatic cts flow control. transmis- sion stops when cts# goes to a logical 1. transmission resumes when the cts# pin returns to a logical 0. feature control register (fcr) this register is only accesible when lcr is set to 0xbf. fctr bit 0-1: user selectable rts# delay or hysteresis for hardware flow control application. after reset, these bits are set to logic 0 to select the next trigger level on the rx fifo trigger level (fcr bit 6-7,table-a). these bits are also associated with emsr bit-4 and 5 for the hysteresis control. see emsr register for more details. fctr bit-2: 0 = select rx input as encoded irda data. 1 = select rx input as active high encoded irda data. fctr bit-3: auto rs485 half duplex direction control. *op1# output is not available in the 872, however, it does change the behavior of the transmit empty interrupt. 0 = transmitter generates an interrupt when transmit holding register becomes empty while transmit shift register is still shifting data out. 1 = enable auto rs485 half duplex direction control. the transmit empty interrupt generation is delayed until the transmitter shift register (tsr) becomes empty. fctr bit 4-5: transmit / receive trigger table select. fctr fctr trigger bit-5 bit-4 table 0 0 table-a (tx/rx) 0 1 table-b (tx/rx) 1 0 table-c (tx/rx) 1 1 table-d (tx/rx)
xr16c872 32 rev. 1.00 visit exar web site at www.exar.com discontinued fctr bit-6: scratch pad register (spr) or emsr select. 0 = scratch pad register (spr) is selected as general read and write register. 16c550 compatible mode. 1 = fifo count register, enhanced mode select reg- ister (emsr). number of characters in transmit or receive holding register can be read via scratch pad register when this bit is set. enhanced mode is selected when it is written into it. fctr bit-7: programmable trigger register select. 0 = receiver programmable trigger level register (trg) is selected. 1 = transmitter programmable trigger level register (trg) is selected. trigger level/fifo count register (trg) this register is only accessible when lcr is set to 0xbf. this register provides the user programmable transmit or receive trigger level from byte 0 to 128 (0xff), and reading the number of data bytes in the transmit or receive fifo. trg bit 0-7: write only. this register sets the user programmable transmit or receive fifo trigger levels. fctr bit-7 must be set and point to the transmitter or receiver prior programming the trigger level. trg bit 0-7: read only. transmit / receive fifo count. number of characters in transmit or receive fifo can be read via this register. fctr bit-7 must be set and point to the transmitter or receiver prior reading the fifo count. enhanced mode select register (emsr) this register is only accessible when lcr is set to 0xbf and fctr bit-6 is set to logic 1. emsr bit-0: write only 0 = receive fifo count register. the scratch pad register (spr) is used to provide the receive fifo count when it is read. 1 = transmit fifo count register. the scratch pad register (spr) is used to provide the transmit fifo count when it is read. example to read the number of character count in tx or rx fifo. in the initialization routine: set lcr to 0xbf ; point to enhanced registers set fctr bit-6 to logic 1 ; swap spr to be fifo counters and ; point to emsr register set lcr to operating parameters - in rx routine - set emsr bit-0 to logic 0 ; set to read rx fifo count read spr ; obtain rx fifo count or - in tx routine - set emsr bit-0 to logic 1 ; read tx fifo count read spr ; obtain tx fifo count emsr bit-1: write only 0 = normal. 1 = alternate receive - transmit fifo count. when emsr bit-0=1 and emsr bit=1, scratch pad register is used to provide the receive - transmit fifo count when it is read every alternate read cycle. the trg bit- 7 will provide fifo count mode information, trg bit- 7=0 receive mode, trg bit-7=1 transmit mode. emsr bit-2: write only this bit is not available in the 872. emsr bit4 and 5 - write only these bits select the rts flow control hysteresis and are associated with fctr bit 0 and 1. the rts hysteresis is reference to the rx fifo trigger level. below table show the 16 selectable hysteresis.
xr16c872 33 rev. 1.00 visit exar web site at www.exar.com discontinued emsr emsr fctr fctr rts hysteresis bit-5 bit-4 bit-1 bit-0 (characters) 0000 next level 0001 +/- 4 0010 +/- 6 0011 +/- 8 0100 +/- 8 0101 +/- 16 0110 +/- 24 0111 +/- 32 1000 +/- 12 1001 +/- 20 1010 +/- 28 1011 +/- 36 1100 +/- 40 1101 +/- 44 1110 +/- 48 1111 +/- 52 emsr bit 6-7: reserved for future use.
xr16c872 34 rev. 1.00 visit exar web site at www.exar.com discontinued 1284 controller the bi-directional parallel data port controller is compatible to ieee standard 1284 interface. the 1284 interface can be programmed as a standard printer port or bi-directional parallel port for high speed data transfer systems. the 1284 interface provides 1284 level ii electrical interface, needing no external transceivers to interface to the parallel port cable. hence, it can connect directly to a printer or a high speed bi-directional parallel device. the 1284 controller supports the following modes of operation. standard centronics interface, forward only bi-directional centronics. parallel port with data fifo. ecp, extended capabilities port, and with 16 byte data fifo in forward and reverse modes, supports run length encoded (rle) de-compression in the reverse mode, however, no compression is sup- ported in the forward mode, and direct memory access transfer capability. epp, enhanced parallel port. on a reset, the device defaults to compatible mode which is the standard pc centronics printer mode in pc computers. the epp, and ecp modes can only be activated by programming the extended control register (ecr), this requires address bit a10=1, which is outside the normal parallel port address in the isa i/o space. the internal timing is designed to operate from a 22.1184 mhz clock which is supplied from an external source on pin xtal1 or by the built-in oscillator circuit with an appropriate crystal. optional capabilities of the ecp specification are set as follows: ecp defined interrupts are pulsed, low true (centronics ack# is non-pulsed, low true). pword size is forced to 1 byte. there is 1 byte in the transmitter that does not affect the fifo full bit (ecp modes). rle compression is not supported in hardware. irq channel is selectable as 5, 7, or 9. dma channel is selectable as 3 fifo threshold is set at 8 (used only for non-dma access to the fifo). port address read/write mode function data 000 r/w 000 data port ecp-afifo 000 w 011 ecp fifo (address) dsr 001 r all status register dcr 002 r/w all control register epp-aport 003 r/w 100 epp port (address) epp-dport 004-007 r/w 100 epp port (data) c-fifo 400 w 010 parallel port data fifo ecp-dfifo 400 r/w 011 ecp fifo (data) t-fifo 400 r/w 110 test fifo cnfg-a 400 r 111 configuration register a cnfg-b 401 r-r/w 111 configuration register b ecr 402 r/w all extended control register
xr16c872 35 rev. 1.00 visit exar web site at www.exar.com discontinued standard definitions forward direction only. compatible mode, centronics or standard mode (spp). reverse direction only. nibble mode: 4 bits at a time using status lines for data hewlett packard bi-tronics. bi-directional. epp: enhanced parallel port, used primarily by non- printer peripherals. ecp: extended capability port, used primarily by latest generation of printers, scanners and external stor age and cd drives for higher data transfer rate. data register (data ) data bit 0-7: for host output cycles in spp mode (ecr mode 000) or ps/2 mode (ecr mode 001), data from the host is registered at the trailing edge of iow#. on host input cycles, data at the peripheral port is passed through to the host data bus. ecp fifo address ( ecp-afifo ) ecp-afifo bit 0-7: this port is only available for programmed i/o (non- dma), and only has significance for host write. data written to this port is stored in the fifo if fifo-f = 0 and will be lost if fifo-f = 1. a 9th fifo bit (tag) is set low on write. a read from this port is the same as a read at 400. data status register ( dsr ) this status register is read-only except for bit-0, and all bits are latched for the duration of ior#. dsr bit-0: if epp mode is not selected, this bit returns logic one. during epp mode, bit-0 will return a high if the epp 10 msecond timeout elapsed during the last epp read or write cycle (this timeout also aborts the epp cycle). this status bit is cleared by exiting epp mode or by the host writing a high to bit-0 of this register. dsr bit 1-2: reserved, logic one. dsr bit-3: the true state of the err# pin. dsr bit-4: the true state of the select pin. dsr bit-5: the true state of the pe pin. dsr bit-6: the true state of the ack# pin. dsr bit-7: the complement of the busy pad. data control register ( dcr ) dcr bit-0: the complement of this bit drives strobe#, and the complement of the pad state is returned for read. dcr bit-1: the complement of this bit drives autofd#, and the complement of the pad state is returned for read. dcr bit-2: this bit drives init#, and the pad state is returned for read. dcr bit-3: the complement of this bit drives selctin#, and the complement of the pad state is returned for read. dcr bit-4: ack interrupt enable set to a high will generate an interrupt when ack# is low. when either returns to a high state, this interrupt source will go in-active. this interrupt is not pulsed. dcr bit-5: peripheral port direction, out = 0 and in = 1.
xr16c872 36 rev. 1.00 visit exar web site at www.exar.com discontinued this bit is forced to logic zero by ecr modes 000 or 010. it can be written only in ecr mode 001, and will maintain that state if the ecr mode is changed to 011, 100, or 110. this bit must be set low for epp mode, which allows the host to control direction with ior# and iow#. the final port direction also drives pdir. dcr bits 6-7: reserved, logic zero. epp address port ( epp-aport ) when epp mode is enabled, a host read or write with this port will result in a data transfer directly to/from the peripheral with slctin# active. direction is set by host read/write and will drive strobe# low during a write if dcr bit 5 (dir) is not set high. epp data port (epp-dport ) when epp mode is enabled, a host read or write with this port will result in a data transfer directly to/from the peripheral with autofd# active. direction is set by host read/write and will drive strobe# low during a write if dcr bit 5 (dir) is not set high. parallel port data ( c-fifo ) this port is available for programmed i/o and dma access. data written to this port is stored in the fifo if fifo-f = 0 and will be lost if fifo-f = 1. data written to this port will be automatically transferred to the peripheral with strobe# handshaking with busy. this port is only defined for write, host reads will interfere with fifo read sequencing. ecp data fifo ( ecp-dfifo ) this port is available for programmed i/o and dma access. data written to this port is stored in the fifo if fifo-f = 0 and will be lost if fifo-f = 1. a 9th fifo bit (tag) is set high on write. data read from this port will undergo de-compression if the fifo tag bit and data bit-7 are both low. the byte containing the rle count is loaded into the rle counter and the succeeding byte in the fifo will be returned to the host rle count + 1 times before the fifo read address is incremented. if a fifo under-run is incurred during host read, the last data byte is returned and fifo-e remains coherent. test fifo ( t-fifo ) this port is available for programmed i/o and dma access. data written to this port is stored in the fifo if fifo-f = 0 and will be lost if fifo-f = 1. during a read cycle from this port a fifo under-run will return last data read and fifo-e remains coherent. configuration register a ( cnfg-a ) this read-only register is available in ecr mode 111 only. cnfg-a bit 0-1: forced to logic zero, this field is dont care for pword = 1 byte. cnfg-a bit-2: when transmitting, there is 1 byte waiting to be trans- mitted that does not affect fifo-f. cnfg-a bit-3: reserved, logic zero. cnfg-a bit 4-6: indicates pword = 1 byte (8-bit implementation). cnfg-a bit-7: indicates ecp interrupts are pulsed. configuration register b ( cnfg-b ) this register is available in ecr mode 111 only, and returns bits 0-5 as logic zero. cnfg-b bit 0-2: in the pnp mode the dma channel is assigned through auto configuration. it defaults to dma 3 in the manual mode. iow# ior# dma x00 000 3 x01 001 3 x10 010 3 x11 011 3 (default)
xr16c872 37 rev. 1.00 visit exar web site at www.exar.com discontinued cnfg-b bit 3-5: in the pnp mode irq assignment is made through auto configuration. manual mode defaults to irq 7. iow# ior# irq 000 001 7 001 001 7 (default) 010 010 7 011 001 7 100 001 7 101 001 7 110 001 7 111 111 7 cnfg-b bit-6: returns the true value of the selected irq pad. cnfg-b bit-7: indicates rle compression is not supported. extended control register ( ecr ) the extended control register has a system reset state of 10010101. the significance of the bits is defined by the ecp specification as: ecr bit-0: this read-only bit returns fifo empty status (fifo-e) and is forced high unless ppf, ecp, or tst mode is selected. 0 = at least one byte of data contains in the fifo. 1 = fifo is empty. ecr bit-1: this read-only bit returns fifo full status (fifo-f) and is forced low unless ppf, ecp, or tst mode is selected. 0 = at least one empty location is available in the fifo. 1 = fifo is full. ecr bit-2: when low, this bit (serviceintr) enables a pulsed inter- rupt and enables dma requests (if bit-3 is set). if the enabled interrupt occurs, this bit is automatically re- turned to a high. the interrupt conditions are: ecr bit-3 = dma dcr bit-5 = direction dma dir condition 0 0 8 empty bytes in the fifo. 0 1 8 filled bytes in the fifo. 1 x dma terminal count (tc). ecr bit-3: this bit disables dma when set low. when set high, a low on serviceintr will enable dma requests. 0 = dma disabled, drqx pin is three-stated. 1 = dma enabled ecr bit-4: when low, this bit (errintren#) enables a pulsed inter- rupt if err# (fault#) is low. the interrupt is only enabled in ecp mode. ecr bit 5-7: this field can be set to any value if the current value is 000 or 001. if the current value is not 000 or 001, then the field can only be written to 000 or 001. the modes are defined as: mode name description 000 spp standard, output only. dcr bit-5 is forced to 0. 001 ps2 bi-directional ps/2 parallel port. fifo is disabled 010 ppf fifoed, output only. dcr bit- 5 is forced to 0. 011 ecp ecp fifoed port with rle de- compression. fifo direction is controlled by dcr bit-5. 100 epp epp mode. 101 - reserved 110 tst fifo test mode. fifo is ac- cessible via tfifo register. 111 cfg configuration a/b register en- able.
xr16c872 38 rev. 1.00 visit exar web site at www.exar.com discontinued operation spp mode this is ecr mode 000 (system reset mode). in this output-only mode the host data is registered to pd[7:0] at the trailing edge of iow#; pdir is driven low; strobe#, autofd#, init#, and selctin# are open-drain; and all timing is managed by the host through dsr and dcr registers. ps2 mode this is ecr mode 001. in this bi-directional mode the host output data is registered to pd[7:0] at the trailing edge of iow#, pdir is driven by dir to allow peripheral data input, autofd#, init#, and selctin# are totem-pole, and all timing is managed by the host through dsr and dcr registers. ppf mode this is ecr mode 010. in this output-only mode the host data is written to the fifo with i/o writes to address 400 or by dma writes; pdir is driven low. fifo data is automatically registered to pd[7:0] whenever the fifo-e bit is low (data available), and timing is generated by controller logic that handshakes strobe# (controller) with busy (peripheral). ecp mode this is ecr mode 011. in this bi-directional mode the host data is written to the fifo with i/o writes to address 000, 400 or dma; pdir is driven by dir (can only be set in ecr mode 001); autofd#, init, and selctin# are totem-pole. i/o writes to address 000 will write a low into the fifo tag bit, while i/o writes to address 400 or dma will insert a high. ecp forward mode (pdir = 0) fifo data is automatically registered to pd[7:0] whenever the fifo-e bit is low (data available), and timing is generated by controller logic that handshakes strobe# (controller) with busy (peripheral). data from the fifo tag bit is output on autofd# after being registered simultaneous with fifo data. ecp reverse mode (pdir = 1) pd[7:0] data and busy are latched into the fifo and tag bit respectively at the trailing edge of autofd# if fifo- f = 0. timing is generated by controller logic that handshakes ack# (peripheral) with autofd# (controller). epp mode this is ecr mode 100. in this bi-directional mode, i/o writes will latch host output data at the trailing edge of iow#, and peripheral input data will be latched at the trailing edge of selctin# or autofd#. pdir, and strobe# are driven by the state of iow# (dcr bits 5 and 0 must be set low). epp mode allows buffered access between the pc bus and the peripheral with timing provided by the peripheral via busy handshake into iochrdy. i/o cycles with address 003 - 007 will immediately drive iochrdy low. strobe# will go low and pd[7:0] is allowed to change (write cycles) after busy has been low for at least 60n second. (this delay may have elapsed prior to cycle initiation), immediately followed by a low driven on selctin# for address 003 or autolf# (datastb*) for address 004 - 007 (read and write cycles). when busy returns high for a minimum of 60n second, iochrdy and the active strobe will be driven high - allowing the host to complete the i/o transaction.
xr16c872 39 rev. 1.00 visit exar web site at www.exar.com discontinued to prevent a system stall, a 10 msecond timeout aborts the cycle if it expires before busy returns high. this timeout also sets bit 0 of dcr, which is cleared by disabling epp mode or writing a high to dcr bit 0. tst mode this is ecr mode 110. this mode allows data to be transferred (read or write in any direction) between the fifo and host at address 400 or dma without activating the control interface (no data is transferred to/from the peripheral). pdir is driven by dir (can only be set in ecr mode 001). performing i/o cycles in this mode allows software to test for the value of fifothreshold (ft) for both output and input directions. cfg mode this is ecr mode 111. this mode enables i/o access to the configuration registers conf-a and conf-b and disables i/o ac- cess to the fifo. irq the module has four sources of interrupt which may be directed to irq5, irq7, irq9 (see conf-b). in pnp mode irq assignment is made through auto configura- tion. 1) when dcr bit 4 (aie) is high and ack# is low the interrupt is active. 2) when ecp mode is active, if ecr bit 4 is low when error transitions low or ecr bit 4 transitions low when fault# is low an interrupt pulse of at least 200n seconds will be generated. 3) in fifo modes (ppf, ecp, or tst) with ecr bit 3 (dma) low, an interrupt pulse of at least 200n seconds will be generated when ecr bit 2 (si) is set low if there are at least 8 empty bytes in the fifo and pdir = 0 or there are at least 8 filled bytes in the fifo and pdir = 1. this interrupt will automatically disable itself by setting ecr bit 2 high. 4) in fifo modes (ppf, ecp, or tst) with (dma request enabled), an interrupt pulse of at least 200n seconds will be generated when tc is received if pd- ack is low. this interrupt will automatically disable itself and the dma request by setting ecr bit 2 high. dma dma cycles occur only between the host and the fifo data port (address 400) for ppf, ecp, or tst modes. drq(1, 2, or 3) is selected through auto configuration in pnp mode and they will be driven high if ecr bit 3 (dma) is high and ecr bit 2 (si) is low when {pdir = 0 and fifo-f = 0} or {pdir = 1 and fifo-e = 0} or tst mode is active. manual mode defaults to drq3. when the selected dackn#(1, 2, or 3) is low, iow# will transfer host data to the fifo and ior# will transfer fifo data to the host. the selected dreqn will be driven low to terminate the dma channel when {pdir = 0 and fifo-f = 1} or {pdir = 1 and fifo-e = 1} or ecr bit 2 (si) goes high (interrupt condition 4 above) or more than 32 consecutive dma data cycles (read or write) have occurred. fifo-f and fifo-e terminated cycles will automatically restart when their state returns low. consecutive cycle termination will automatically restart because the counter is reset when the selected dackn# goes high. tc terminated cycles can only be restarted by the host setting ecr bit 2 (si) low again. rle the module does not support run length encoding (rle) compression (indicated by the 0 in conf-b bit 7) but does support rle de-compression on the receiv- ing side. the host may send compressed data to the peripheral by writing the rle length byte (bit 7 = 0) to address 000 (note: dma cannot be used for this byte) which will place a zero into the fifo tag bit. this must be followed immediately by the data byte being written to the fifo at address 400. these bytes will be transferred to the peripheral in the normal manner. de-compression takes place if pdir = 1 when data is read from the fifo at address 000, 400 or dma. when a byte is read from the fifo, bits 0-6 (length) are placed in a counter if data bit-7 and the fifo tag bit are both low. the subsequent byte in the fifo (data) is pre- sented to the host count + 1 times before the fifo read pointer is advanced.
xr16c872 40 rev. 1.00 visit exar web site at www.exar.com discontinued 1284 controller registers description a10 a2 a1 a0 register d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecp-afifo 0 0 0 1 dsr busy acke pe select err# 1 1 1 0 0 1 0 dcr 0 0 dir int selctin# init# autofd# strobe# enable 0 0 1 1 epp-aport ap-7 ap-6 ap-5 ap-4 ap-3 ap-2 ap-1 ap-0 0 1 0 0 epp-dport pda-7 pda-6 pda-5 pda-4 pda-3 pda-2 pda-1 pda-0 0 1 0 1 epp-dport pdb-7 pdb-6 pdb-5 pdb-4 pdb-3 pdb-2 pdb-1 pdb-0 0 1 1 0 epp-dport pdc-7 pdc-6 pdc-5 pdc-4 pdc-3 pdc-2 pdc-1 pdc-0 0 1 1 1 epp-dport pdd-7 pdd-6 pdd-5 pdd-4 pdd-3 pdd-2 pdd-1 pdd-0 1 x 0 0 conf-a ecp 0010 fifo-f 0 0 int type 1 x 0 1 conf-b rle irq irq irq irq dma dma dma input sel-2 sel-1 sel-0 sel-2 sel-1 sel-0 1 x 1 0 ecr mode mode mode fault dma service fifo fifo sel-2 sel-1 sel-0 enable en/dis int full empty
xr16c872 41 rev. 1.00 visit exar web site at www.exar.com discontinued centronics, spp signal descriptions signal signal description name type strobe# o active low. indicates valid data is on the data lines. autofd# o active low. instructs the printer to automatically insert a line feed for each carriage return. selctin# o active low. used to indicate to the printer that it is selected. init# o active low. used to reset the printer ack# i a low asserted pulse used to indicate that the last character was received. busy i a high signal asserted by the printer to indicate that it is busy and cannot take data. pe i a high signal indicated that printer paper is empty. select i a high signal indicates that printer is online. err# i asserted low to indicate that some error condition exists. pd0-pd7 o data.
xr16c872 42 rev. 1.00 visit exar web site at www.exar.com discontinued nibble mode signal descriptions signal signal nibble mode description name type name strobe# o strobe# not used for reverse data transfer. autofd# o hostbusy host nibble mode handshake signal. set low to indicate host is ready for nibble. set high to indicate nibble has been received. selctin# o 1284active set high when host is in a 1284 transfer mode. init# o init# not used for reverse data transfer. ack# i ptrclk set low to indicate valid nibble data, set high in response to hostbusy going high. busy i ptrbusy used for data bit-3, then bit-7. pe i ackdatareq used for data bit-2, then bit-6. select i xflag used for data bit-1, then bit-5. err# i dataavail# used for data bit-0, then bit-4. pd0-pd7 o not used. nibble mode data transfer cycle 1. host signals ability to take data by asserting hostbusy low. 2. peripheral responds by placing first nibble on status lines. 3. peripheral signals valid nibble by asserting ptrclk low. 4. host sets hostbusy high to indicate that it has received the nibble and is not ready for another nibble. 5. peripheral sets ptrclk high to acknowledge host.
xr16c872 43 rev. 1.00 visit exar web site at www.exar.com discontinued epp mode signal descriptions signal signal epp mode description name type name strobe# o write# active low. indicates a write operation, high for a read cycle autofd# o datastb# active low. indicates a data-read or data-write operation is in process. selctin# o addrstb# active low. indicates an address-read or address-write opera tion is in process. init# o reset# active low. peripheral reset. ack# i intr# peripheral interrupt. used to generate an interrupt to the host. busy i wait# handshake signal. when low it indicates that is okay to start a cycle, when high it indicates that it is okay to end the cycle. pe i user defined not used. select i user defined not used. err# i user defined not used. pd0-pd7 o ad0-ad7 bi-directional address / data lines. epp mode data transfer cycle 1. program executes an i/o write cycle to epp data port-4. 2. the write# line is asserted and the data is output to the parallel port. 3. the datastb# is asserted, since write# is asserted low. 4. the port waits for the acknowledge from the peripheral, write# deasserted. 5. the datastr# is deasserted and epp cycle ends. 6. write# is asserted low to indicate that the next cycle may begin.
xr16c872 44 rev. 1.00 visit exar web site at www.exar.com discontinued ecp mode signal descriptions signal signal ecp mode description name type name strobe# o hostclk used with periphack to transfer data or address information in the forward direction. autofd# o h ostack provides command / data status in the forward direction. used with periphclk to transfer data in the reverse direction. selctin# o 1284active set high when host is in a 1284 transfer mode. init# o reversereq# driven low to put the channel in reverse direction. ack# i periphclk used with hostack to transfer data in the reverse direction. busy i periphack used with hostclk to transfer data or address information in the forward direction. provides command / data status in the reverse direction. pe i ackreverse# driven low to acknowledge reverserequest. select i xflag extensibility flag. err# i periphreq# set low by peripheral to indicate that reverse dat is available. pd0-pd7 i/o d0-d7 bi-directional data lines. ecp mode forward data and command transfer cycle 1. host places data on the data lines and indicates a data cycle by setting hostack high. 2. host asserts hostclk low to indicate valid data. 3. peripheral acknowledge host by setting periphack high. 4. host sets hostclk high. this is the edge that should be used to clock the data in to the peripheral. 5. peripheral sets periphack low to indicate that it is ready for the next byte. 6. the cycle repeats, but this time it is command cycle because hostack is low. ecp mode reverse data and command transfer cycle 1. the host requests a reverse channel transfer by setting reversereq# low. 2. the peripheral signals that it is okay to proceed by setting ackreverse# low. 3. the peripheral places data on the data lines and indicates a data cycle by setting periphack high. 4. peripheral asserts periphclk low to indicate valid data. 5. host acknowledges by setting hostack high. 6. peripheral sets periphclk high. this is the edge that should be used to clock the data in to the host. 7. host sets hostack low to indicate that it is ready for the next byte. 8. the cycle repeats, but this time it is a command cycle because periphack is low.
xr16c872 45 rev. 1.00 visit exar web site at www.exar.com discontinued uart registers reset conditions register reset state rhr 0xxx, x=random thr 0xxx, x=random ier 0x00 fcr 0x00 isr 0x01 lcr 0x00 mcr 0x00 lsr 0x60 msr 0xx0, x=state of input pins spr 0xff dll 0xxx, x=random dlm 0xxx, x=random trg 0x00 fctr 0x00 efr 0x00 xon-1 0x00 xon-2 0x00 xoff-1 0x00 xoff-2 0x00 emsr 0x00 output reset state signals tx a-b logic 1 rts# a-b logic 1 dtr# a-b logic 1 1284 controller register reset conditions register reset state ecp-afifo dsr 0xxx, x=state of input pins dcr bit 0-4=0 epp-aport epp-dporta epp-dportb epp-dportc epp-dportd conf-a bit 0-7=0 conf-b bit 0-5=0 ecr 0x95
xr16c872 46 rev. 1.00 visit exar web site at www.exar.com discontinued absolute maximum ratings supply range -0.5 to 7 volts voltage at any pin -0.5 v to vcc+0.5 v operating temperature -40c to +85c storage temperature -65c to +150 package dissipation (100-pqfp) 500 mw * thermal resistance: theta-ja 45 c/watt theta-jc 12 c/watt dc electrical characteristics t a =0 - 70 c (-40 - +85c for iq package), vcc=3.3 or 5.0 v 10% unless otherwise specified. symbol parameter limits limits units conditions 3.3 5.0 min max min max v ilck clock input low level 0.6 0.6 v v ihck clock input high level 2.4 3.0 v vcc v il input low level -0.5 0.8 -0.5 0.8 v v ih input high level 2.0 2.2 vcc v v ol output low level on type o outputs 0.4 v i ol = 6 ma v ol output low level on type ot24 outputs 0.4 v i ol = 18ma v ol output low level on type io14 outputs 0.4 v i ol = 14 ma v ol output low level on type i024 outputs 0.4 v i ol = 18ma v ol output low level on type o outputs 0.4 v i ol = 6ma v ol output low level on type ot24 outputs 0.4 v i ol = 9ma v ol output low level on type io14 outputs 0.4 v i ol = 14ma v ol output low level on type i024 outputs 0.4 v i ol = 9ma v oh output high level on type o outputs 2.4 v i oh = -6 ma v oh output high level on type ot24 outputs 2.4 v i oh = -12 ma v oh output high level on type io14 outputs 2.4 v i oh = -14 ma v oh output high level on type i024 outputs 2.4 v i oh = -12 ma v oh output high level on type o outputs 2.0 v i oh = -1.5ma v oh output high level on type ot24 outputs 2.0 v i oh = -3ma v oh output high level on type io14 outputs 2.0 v i oh = -10ma v oh output high level on type i024 outputs 2.0 v i oh = -3ma i il input leakage 10 10 ua i cl clock leakage 10 10 ua i cap input capacitance 5 5 pf r in internal pull up/down resistance 55 185 k ohms i cc supply current 5.5 10 ma 4-7 ma typ.
xr16c872 47 rev. 1.00 visit exar web site at www.exar.com discontinued symbol parameter limits limits units conditions 3.3 5.0 min max min max host interface and uart ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. t 1cw clock pulse duration 20 20 ns t 2fq oscillator/clock frequency tbd 24 mhz t 3as address setup time 10 5 ns t 4ah address hold time 10 5 ns t 5rd ior# strobe width 50 25 ns t 6dy read/write cycle delay 50 50 ns t 7da delay from ior# to data 35 25 ns t 8dh data disable time 25 15 ns t 9wr iow# strobe width 40 40 ns t 10ds data setup time 20 15 ns t 11dh data hold time 50 35 ns t 12d delay from iow# to modem output 50 50 ns 100 pf load t 13d delay from modem input to msr interrupt 50 35 ns 100 pf load t 14d delay from ior# to reset msr interrupt 50 35 ns 100 pf load t 15d delay from stop bit to set rx interrupt 1 1 rclk t 16d delay from ior# to reset interrupt 200 200 ns 100 pf load t 17d delay from stop bit to set tx interrupt 100 100 ns t 18d delay from int reset to transmit start 8 24 8 24 rclk t 19d delay from iow# to reset interrupt 175 175 ns t rst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 rclk
xr16c872 48 rev. 1.00 visit exar web site at www.exar.com discontinued symbol parameter limits limits units conditions 3.3 5.0 min max min max 1284 controller ac electrical characteristics t a =0 - 70c (-40 - +85c for industrial grade packages), vcc=3.3 - 5.0 v 10% unless otherwise specified. t20 pd7-pd0, strobe#, autofd#, init, 100 ns slctin# delay from iow# inactive t21 interrupt delay from ack# 60 ns t22 interrupt pre-charge pulse at release 10 ns t23 tc pulse width 60 ns t24 tc active to drqx inactive 100 ns t25 drqx active to dackx# active 0 ns t26 drqx inactive delay from dackx# 100 ns active t27 pd7-pd0 setup to strobe# active 600 ns t28 strobe# width 600 ns t29 pd7-pd0 hold from strobe# inactive 450 ns t30 pd7-pd0 hold from busy inactive 80 ns t31 strobe# active to busy active 500 ns (handshake) t32 busy inactive to strobe# active 680 ns (cycle delay) t33 pd7-pd0, autofd# setup to strobe# 0 60 ns active t34 pd7-pd0, autofd# hold from busy 80 180 ns active t35 strobe# inactive to busy inactive 0 ns t36 busy inactive to #strobe active 80 200 ns t37 #strobe active to busy active 0 ns t38 busy active to #strobe inactive 80 180 ns t39 pd7-pd0, busy setup to ack# active 0 ns t40 pd7-pd0 data hold from autofd# 0 ns active t41 ack# inactive to autofd# active 80 200 ns t42 autofd# active to ack# active 0 ns t43 ack# active to autofd# inactive 80 200 ns t44 autofd# inactive to ack# inactive 0 ns t45 host address setup to iow# active 40 ns t46 host address hold from iow# active 10 ns t47 host data setup to iow# active 0 20 ns t48 host data hold from iow# active 0 ns t49 iow# active to iochrdy low 0 20 ns t50 iochrdy high to host terminate 10 ns (iow# inactive)
xr16c872 49 rev. 1.00 visit exar web site at www.exar.com discontinued symbol parameter limits limits units conditions 3.3 5.0 min max min max t51 iow# inactive to host command active 40 ns (iow# or ior#) t52 iochrdy pre-charge width at release 10 ns t53 host address setup to ior# active 40 ns t54 host address hold from ior# active 10 ns t55 host data setup to ior# inactive 0 20 ns t56 host data hold from ior# inactive 0 ns t57 ior# active to iochrdy low 0 20 ns t58 iochrdy high to host terminate 10 ns (ior# inactive) t59 ior# inactive to host command active 40 ns (iow# or ior#) 1284 controller ac electrical characteristics (continue)
xr16c872 50 rev. 1.00 visit exar web site at www.exar.com discontinued isa bus read timing d0-d7 t7da t8dh xr872rd aen a0-a15 ior# t4ah t5rd t3as valid address active data valid t6dy external clock timing t2fq t1cw external clock t1cw
xr16c872 51 rev. 1.00 visit exar web site at www.exar.com discontinued isa bus write timing d0-d7 t11dh xr872wr aen a0-a15 iow# t4ah t9wr t3as active t10ds t6dy data valid valid address modem input/output timing iow# rts# dtr# outputs cd# cts# dsr# inputs int ior# ri# t12d t13d t14 d xr872md active active chan g e of state chan g e of state active active active chan g e of state chan g e of state chan g e of state active active t13d t13d
xr16c872 52 rev. 1.00 visit exar web site at www.exar.com discontinued receive data timing in dma mode 0 stop bit parity bit data bits (5-8) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 5 data bits 6 data bits 7 data bits start bit rx next data start bit int ior# t15d t16d 16 baud rate clock xr872rx active receive data timing in fifo and dma mode 1 rx data fills rx fifo int ior# active rx fifo fills to trigger level unload rx fifo data active receive data ready int receive data time-out int ~4 characters delay xr872rfifo byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte
xr16c872 53 rev. 1.00 visit exar web site at www.exar.com discontinued transmit data timing stop bit parity bit data bits (5-8) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 5 data bits 6 data bits 7 data bits start bit tx next data start bit int (thr empty interrupt) t17d t19d 16 baud rate clock xr872tx iow# t18d active active d0-d7 data byte 1 data byte 3 active active active data byte 2 active byte byte byte byte byte byte byte byte byte tx is sent and fifo g ets empty to tri gg er level xr872tfifo byte byte byte byte byte byte tx fifo g ets more data byte int (thr empty interrupt) iow# tx data fills fifo transmit fifo operation
xr16c872 54 rev. 1.00 visit exar web site at www.exar.com discontinued infrared transmit timing infrared receive timing tx character data bits start stop 0000 0 11 111 tx irtx bit time 1/2 bit time 3/16 bit time rx character data bits start stop 0000 0 11 111 rx irrx bit time 0-1 16x clock delay xr16ir
xr16c872 55 rev. 1.00 visit exar web site at www.exar.com discontinued parallel port timing in spp, ps/2 mode host dma timing in ecp mode iow# pd0-7 ack# irqx 7836spp t20 t21 t8 t22 tc drqx aen dackx# 7836dma iow#, ior# t 23 t 24 t 25 t 26
xr16c872 56 rev. 1.00 visit exar web site at www.exar.com discontinued parallel port fifo timing t 27 t 28 t 29 pd0-pd7 strobe# busy 7836ppf t 31 t 30 t 32 parallel port forward timing in ecp mode pd0-7 strobe# busy 7836ecf autofd# t33 t34 t35 t36 t37 t38 t35
xr16c872 57 rev. 1.00 visit exar web site at www.exar.com discontinued parallel port reverse timing in ecp mode address or data write timing in epp mode pd0-7 ack# autofd# 7836ecr busy t39 t40 t41 t42 t43 t44 t41 a0-2, a10 7836epw d0-d7 iochrdy iow# t45 t46 t47 t48 t49 t50 t51 t52
xr16c872 58 rev. 1.00 visit exar web site at www.exar.com discontinued address or data read timing in epp mode a0-2, a10 7836epr d0-d7 iochrdy ior# t53 t54 t55 t56 t57 t58 t59 t52
xr16c872 59 rev. 1.00 visit exar web site at www.exar.com discontinued
xr16c872 60 rev. 1.00 visit exar web site at www.exar.com discontinued notice exar corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publicatio has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circum- stances. copyright 2003 exar corporation. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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